1. Field of the Invention
The present invention relates to a bit synchronization circuit, and more particularly to a bit synchronization circuit for automatically adjusting the timing of input data having jitter.
2. Description of the Related Art
In the art of digital signal transmission, it is customary to generate a higher-level digital signal by multiplexing a plurality of lower-level digital signals in a transmitting station, send the higher-level digital signal from the transmitting station via a transmission link to a receiving station, and demultiplex the higher-level digital signal back into a plurality of lower-level digital signals in a receiving station. In order for the receiving station to recognize the received data correctly, it is necessary that the transmitting and receiving stations be synchronized with each other. Conventional bit synchronization circuits attempt to synchronize the transmitting and receiving stations with each other by automatically adjusting the timing of the received data.
FIG. 1 of the accompanying drawings schematically shows a conventional bit synchronization circuit which has been proposed heretofore. In the conventional bit synchronization circuit shown in FIG. 1, a reference clock signal 10 is supplied to a multiphase clock generator 11, which generates m-phase clock signals 12 that are out of phase with each other. The m-phase clock signals 12 are applied to a clock selection circuit 13 and a selector 14. The selector 14 outputs a clock signal 16 which is alternatively selected from the m-phase clock signals 12 based on a clock selection signal 15 generated by the clock selection circuit 13. Burst input data 17 is supplied to a data input (D) terminal of a D-type flip-flop (hereinafter referred to as "D-FF") 18 and the clock selection circuit 13. The clock signal 16 is applied to a clock input (C) terminal of the D-FF 18. In synchronism with a falling edge of the clock signal 16, the D-FF 18 latches the burst input data 17, and outputs a timing adjustment signal 19 from a data output (Q) terminal thereof.
The clock selection circuit 13 comprises a phase comparator 20, a decoder 21, a phase adjuster 22, and a selection clock counter 23. The phase comparator 20 has a D terminal supplied with the m-phase clock signals 12 and a C terminal supplied with the burst input data 17. The phase comparator 20 compares the phases of the m-phase clock signals 12 and the burst input data 17 with each other, and outputs phase difference information with respect to each of the m-phase clock signals 12 from the Q terminal.
The decoder 21 converts the phase difference information supplied from the phase comparator 20 into a clock name representative of an optimum clock phase corresponding to an edge of the input data 17. The phase adjuster 22 generates phase transition information to be controlled depending on the phase difference between the clock selection signal 15 indicative of the presently selected clock phase and the optimum clock phase at the edge of the input data 17. The generated phase transition information is supplied from the phase adjuster 22 to a count-up/down input (U/D) terminal of the selection clock counter 23. The selection clock counter 23 has a C terminal supplied with the burst input data 17, an initial value input (A) terminal supplied with selected clock information 25 from a clock phase holder 24, and a load input (L) terminal supplied with an initial value input signal from a memory controller 26. When the initial value input signal is of a logic level "H", the selection clock counter 23 outputs, from a Q terminal thereof, a clock selection signal which represents the selected clock information entered from the A terminal. While the burst input data 17 is being applied to the bit synchronization circuit, the clock phase holder 24 is supplied with the clock selection signal 15 indicating the presently selected clock phase, and applies the selected clock information 25 indicating the clock selected immediately before the burst input data 17 is applied, to the A terminal of the selection clock counter 23. The clock phase holder 24 is controlled by the memory controller 26.
The bit synchronization circuit shown in FIG. 1 operates as follows: When the reference clock signal 10 is supplied to the multiphase clock generator 11, the multiphase clock generator 11 generates and supplies m-phase clock signals 12 to the clock selection circuit 13 and the selector 14. In the clock selection circuit 13, the phase comparator 20 compares the phases of each of the m-phase clock signals 12 and the burst input data 17 with each other, and supplies phase difference information to the decoder 21. The decoder 21 converts the phase difference information into a clock name representative of an optimum clock signal to be selected among the m-phase clock signals 12 depending on the phase status of the present input data 17. The phase adjuster 22 generates phase transition information to be controlled between the clock name and the clock selection signal 15 indicating the presently selected clock signal. For example, if the clock signal to be selected is to remain as it is, then the phase adjuster 22 generates phase transition information representing "0". If the clock signal to be selected is to be shifted by a phase corresponding to "+1", then the phase adjuster 22 generates phase transition information representing "+", and if the clock signal to be selected is to be shifted by a phase corresponding to "-1", then the phase adjuster 22 generates phase transition information representing "-".
The selection clock counter 23 generates a counted-up clock selection signal 15 in synchronism with the input data 17 when the phase transition information is "+", a counted-down clock selection signal 15 in synchronism with the input data 17 when the phase transition information is "-", and a clock selection signal 15, which remains unchanged, in synchronism with the input data 17 when the phase transition information is "0". A clock signal represented by the clock selection signal 15 is applied to the selector 14. Based on the clock selection signal 15, the selector 14 outputs a clock signal 16 alternatively selected from the m-phase clock signals 12. The input data 17 is adjusted in timing by the D-FF 18 in synchronism with a falling edge of the selected clock signal 16, and outputted as a timing-adjusted signal 19 from the D-FF 18. A clock signal which is optimum for the previous period is held as an initial value by the clock phase holder 24. Based on the initial clock signal held by the clock phase holder 24, the selection clock counter 23 is initialized at a predetermined timing by the memory control circuit 26. Therefore, even when bit synchronization is required due to a reduction in the transmission link error rate, such bit synchronization can quickly be completed.
Details of the above bit synchronization circuit are disclosed in Japanese laid-open patent publication No. 10-271101 entitled "Timing synchronization circuit", for example.
Japanese laid-open patent publication No. 56-104557 discloses a bit synchronization circuit in which a delayed clock produced by delaying an edge of edge information of a string of two-phase-modulated bit data appropriately from an edge of input data is added to the input data, and the phase is compared by a mask circuit. With the disclosed arrangement, even if the edge information is lost due to a transmission error of the input data, an edge of the delayed clock can be used instead of the edge of the input data that is lost.
Japanese patent publication No. 7-28277 shows a bit synchronization circuit in which differential frequency information is generated based on an error signal produced by comparing the phase of burst input data and the phase a reference clock signal with each other, and the generated differential frequency information and the error signal are accumulated. The differential frequency information and the error signal which are accumulated are combined to variably control the frequency-division ratio of a variable frequency divider, so that even when no input data is supplied, bit synchronization can be controlled based on preceding burst input data. Furthermore, in an initial stage of the input data, the phase difference for bit synchronization is not increased, allowing bit synchronization to be controlled stably.
In the conventional bit synchronization circuits proposed based on the disclosure of Japanese laid-open patent publication No. 10-271101 and Japanese laid-open patent publication No. 56-104557, the phase of an edge of the input data and the phase of the presently selected clock signal are compared with each other, and the phase of a next clock signal is selected depending on the phase difference. Specifically, the clock phase corresponding to the edge phase of the present input data is extracted, and the timing of next input data is adjusted with a clock signal which has the extracted clock phase. Therefore, when the phase of an edge of the present input data and the phase of an edge of the next input data differ from each other owing to a jitter distribution in the input data, a margin available for adjusting the timing of the next input data is greatly reduced, resulting in a higher data error probability. According to the disclosure of Japanese patent publication No. 7-28277, the differential frequency information and the error signal are accumulated simply to avoid an increase in the phase difference through the phase comparison with hypothetical input data in the absence of input data. Consequently, if the input data itself has a jitter distribution, then when the phase of an edge of the present input data and the phase of an edge of the next input data differ from each other, a margin available for adjusting the timing of the next input data is greatly reduced.
As described above, the conventional bit synchronization circuits process the phase of an edge of the input data and the present clock phase to determine a next clock phase. However, the conventional bit synchronization circuits fail to adjust the timing of input data independently of a jitter distribution in the input data. Ideally, the timing of the input data is required to be adjusted in timed relation to the phase of the center of an opening of an eye pattern (hereinafter referred to as "eye").